This application claims benefit of priority under 35USC xc2xa7119 to Japanese Patent Application No. 2000-68971, filed on Mar. 13, 2000, the contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates generally to a clock buffer circuit for generating a pulse every up and down edges of an inputted clock signal, and an interface and synchronous type semiconductor memory device using the clock buffer circuit.
2. Description of Related Art
Typical synchronous type semiconductor memory devices, e.g., synchronous type SRAMs (Static Random Access Memories), use (1) a system driven by increasing its operating frequency, or (2) a system for increasing its data transfer efficiency without changing its operating frequency, in order to realize accelerating.
The synchronous semiconductor memory devices using the system for increasing the data transfer efficiency use a clock buffer circuit for generating a signal synchronized with an inputted clock signal and a signal obtained by inverting the clock signal. In synchronism with the output of the clock buffer, data are transferred.
The construction of a conventional synchronous type semiconductor memory device using a clock buffer circuit is shown in FIG. 8. This synchronous type semiconductor memory device comprises a memory array (not shown), input buffers 201 and 202, a clock buffer circuit 70 and a register circuit 80.
The clock buffer circuit 70 comprises two inverters connected in series. The clock buffer circuit 70 is designed to receive a clock signal CLK from the outside to output a common mode signal having the same phase as that of the clock signal, and an inverted signal having a phase shifted by 180 degrees from the phase of the clock signal.
The register circuit 80 comprises master latch circuits 81 and 82, latch circuits 83 and 84, and slave latch circuits 85 and 86. The register circuit 80 is designed to latch addresses, data or control input signals, which have been inputted via the input buffers 201 and 202, on the basis of the output of the clock buffer circuit 70, and then, transmit the address, data or control input signals to the memory cell array. The register circuit 80 is provided for each address signal, data input signal and control input signal.
The master latch circuits 81 and 82, and the slave latch circuits 85 and 86 have the same construction. For example, as shown in FIG. 9(a), the circuit 81 comprises a clocked inverter for receiving two clocks CLK1 and CLK2. As shown in FIG. 9(b), the clocked inverter 81 comprises two P-channel MOS transistors 81a and 81b, which are connected in series between a driving power supply and an output terminal OUT, and two N-channel MOS transistors 81c and 81d which are connected in series between a ground power supply and the output terminal OUT. An input signal IN is applied to the gate of the P-channel MOS transistor 81a, the source of which is connected to the driving power supply, and to the gate of the N-channel MOS transistor 81d, the source of which is connected to the ground power supply. The clock CLK1 is applied to the gate of the P-channel MOS transistor 81b, and the clock CLK2 having the opposite phase to that of the clock CLK1 is applied to the gate of the N-channel MOS transistor 81c. Therefore, when the master latch circuit and the slave latch circuit are in closed states, the output has high impedance.
The latch circuits 83 and 84 have the same construction. For example, as shown in FIG. 10, the latch circuit 83 comprises two inverters 83a and 83b which are connected in series, and the input terminal of the inverter 83a and the output terminal of the inverter 83b are commonly connected to a node, the potential of which is to be held.
The operation of the conventional synchronous type semiconductor memory device shown in FIG. 8 will be described below.
The switching actions of the master latch circuit 81 and slave latch circuit 86 are designed to be opposite to the switching actions of the master latch circuit 82 and slave latch circuit 85.
Assuming now that the clock signal from the outside has an xe2x80x9cLxe2x80x9d level, the master latch circuit 81 and the slave latch circuit 86 are in a through state, whereas the master latch circuit 82 and the slave latch circuit 85 are in a closed state. Therefore, an external input signal, such as an address, at this time is transmitted to the slave latch circuit 85 via an input buffer 2 and the master latch circuit 81. However, since the slave latch circuit 85 is in the closed state, i.e., since the output is in a high impedance state, an external output signal is held in the latch circuit 83 without being transmitted to the memory cell. Since the slave latch circuit 86 is in the through state at this time, data having been held in the latch circuit 84 are transmitted to the memory cell via the slave latch circuit 86.
Thereafter, when the level of the clock signal CLK from the outside changes from the xe2x80x9cLxe2x80x9d level to an xe2x80x9cHxe2x80x9d level, the output of the clock buffer changes, so that the slave latch circuit 85 is in the through state and the slave latch circuit 86 is in the closed state. Therefore, the external input signal having been held in the latch circuit 83 is transmitted to the memory cell. At this time, the master latch circuit 81 is in the closed state, so that the variation in output of the input buffer 202 is not transmitted to the slave latch circuit 85 even if the output of the input buffer 202 varies. At this time, since the master latch circuit 82 is in the through state, the variation in output of the input buffer 202 is transmitted to the latch circuit 84 to be held therein.
Thereafter, when the level of the clock signal CLK from the outside changes from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d, the master latch circuit 81 and the slave latch circuit 86 are in the through state, and the master latch circuit 82 and the slave latch circuit 85 in the closed state. Thus, the signal value having been held in the latch circuit 84 is transmitted to the memory cell via the slave latch circuit 86.
As described above, the system shown in FIG. 8 operates in synchronism with both of the up edge (the variation from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level) and down edge (the variation from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level) of the clock signal CLK from the outside.
However, if the above described conventional clock buffer circuit 70 is used, two sets of master latch circuits and slave latch circuits must be provided for a single external input signal. For that reason, with the increase of the capacity of semiconductor memory devices (i.e., the increase of address input signals and data input signals) and with the increase of control input signals corresponding to various functional operations, there are problems in that the chip size is very large, the load of the clock buffer increases, and electric power consumption is great.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a clock buffer circuit capable of suppressing the increase of the chip size and decreasing electric power consumption even if the capacity increases or even if the functional operations are varied, and an interface and synchronous type semiconductor memory device having the clock buffer circuit.
In order to accomplish the aforementioned and other objects, according to a first aspect of the present invention, a clock buffer circuit of a semiconductor integrated circuit comprises: a first delay circuit for receiving a first clock signal; a first switching circuit for carrying out a switching action on the basis of an output of the first delay circuit to pass the first clock signal therethrough in accordance with the switching action of the first switching circuit to output the first clock signal; a second delay circuit for receiving a second clock signal which is obtained by inverting the first clock signal; and a second switching circuit for carrying out a switching action on the basis of an output of the second delay circuit to pass the second clock signal therethrough in accordance with the switching action of the second switching circuit to output the second clock signal, wherein the switching action of the second switching circuit is opposite to the switching action of the first switching circuit, and output terminals of the first and second switching circuits are commonly connected.
According to a second aspect of the present invention, a clock buffer of a semiconductor integrated circuit comprises: a first inverter for receiving a first clock signal to output a second signal which is obtained by inverting the first clock signal; a second inverter for receiving the second clock signal to output a third clock signal which has the same phase as that of the first clock signal; a first delay circuit for receiving the third clock signal; a first switching circuit for carrying out a switching action on the basis of an output of the first delay circuit to pass the third clock signal therethrough in accordance with the switching action of the first switching circuit to output the third clock signal; a second delay circuit for receiving the second clock signal; and a second switching circuit for carrying out a switching action on the basis of an output of the second delay circuit to pass through the second clock signal therethrough in accordance with the switching action of the second switching circuit to output the second clock signal, wherein the switching action of the second switching circuit is opposite to the switching action of the first switching circuit, and output terminals of the first and second switching circuits are commonly connected.
According to the present invention, an interface comprises the above described clock buffer circuit and a register which comprises: a master latch circuit for incorporating an input signal on the basis of the output and inverted output of the clock buffer circuit; a first latch circuit for holding an output of the master latch circuit; a slave latch circuit for incorporating an output of the first latch circuit on the basis of the output and inverted output of the clock buffer circuit; and a second latch circuit for holding an output of the slave latch circuit.
According to the present invention, a synchronous type semiconductor memory device includes a memory cell array and the above described interface, wherein the interface is used for accessing the memory cell array.